'Program Memory' and 'Data Memory' blocks use modules called 'PMem' and 'DMem' respectively which were essentially Xilinx memory blocks generated using IPCore. Modeling in HDL and Simulation Using Xilinx ISE 14. Cache: Direct mapping schemeįollowing is the block diagram of the implementation: Regarding memory blocks View EE 118 Lab B Report.docx from EE 118 at Merritt College. The code works so far only for addition of positive numbers. Numbers are represented using IEEE-754 standard. The repository contains test bench for every block, as well as for main modules (debug_1.v and debug_2.v).įloating-point operations (Work in progress)įloating_point.v contains code for performing floating point addition. ![]() This repository is Verilog description of a 16 bit MIPS processor. 16-bit MIPS (Microprocessor Without Interlocked Pipleline Stages)
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